UEFS - MPEG-2 AAC-LC Audio Decoder The team has been developping a MPEG-2 AAC-LC decoder. The main functions of such IP-core are to find the description of the quantized audio spectra in the input bitstream (from an AAC audio file – ISO 13818-7), decode the quantized values and other reconstruction data, reconstruct the quantized spectra, process the reconstructed spectra in order to recover the original signal spectra, and convert the frequency domain spectra to the time domain.   UFC - Java Optimized Processor with Debug Support Due to the constant increase of integration on embedded electronic devices, testing and debugging such systems became more complex. Therefore, the purpose of this project is to implement the debug support for a Java Optimized Processor (JOP), in order to alleviate the difficulties faced by developers of software for the system. The debug support is incorporated by the IEEE 1149.1 interface, On-Chip Debug and Built-In Self-Test.   UFCG - Speaker Verification (SPVR) The Speaker Verification IP-Core is responsible for verifying whether a speaker is who he or she claims to be or not. The verification is done by comparing a set of coefficients, extracted in real time from his/her voice, with a set of coefficients (a codebook) previously obtained during a speaker system-training phase. So, there are three possible responses: Accepted, Rejected or Unknown.   UFPA - Stepper Motor Programmable Controller   UFPB - Biological Signal and Medical Images Lossless Compressor The IP-Core named BSMILC (Biological Signal and Medical Image Lossless Compressor) is justified by the large amount of data generated in medical applications, mainly in portable devices, reducing it in more than half. As such systems are typically used to assist in medical diagnosis, a lossless compression method becomes essential, avoiding distortions and, therefore, false-diagnosis.   UFPE - Direct Memory Access Controller - DMA Controller   UFPE - McBSP Controller   UFRN - Successive Approximation ADC This project is tackled by under-graduate students and aims to design and fabricate a low-power 10 bits ADC using a successive approximation technique. The circuit includes a voltage reference, a comparator, a DAC, and a successive approximation register (SAR). Due to mixed-signal nature of the circuit, 2 design steps will be followed: fabrication of the analog part while the SAR is implemented in FPGA and fabrication of the entire system.   UFS - Multimedia Interface Transmitter IP HDMI is a compact audio/video interface for transmitting uncompressed digital data. It represents a digital alternative to consumer analog standards, such as composite video, S-Video, etc. HDMI system architecture is defined to consist of transmitters, embedded in devices such as Blu-ray players; and receivers, embedded in devices such as TV. The purpose of this project is the development of HDMI transmitter to be used in multimedia platforms.   UFSC/DCT - 2D – Design and Prototyping of an IP-Core for Encoding Images in JPEG Format   UFSC/LCI - Radio Frequency Controller The LCI-UFSC project consists of three IPs: an energy processor (EP), a low noise amplifier (LNA) and a mixer. A piezogenerator extracts the vibrational energy of the environment and the EP circuitry converts, regulates, and stores it in a battery device for later use of a sensing and/or communication circuitry. The LNA and mixer, basic building blocks of any transceiver, operate in the ISM band at 2.4 GHz. Both the LNA and the mixer can be used in a self -powered wireless communication system.   UFSM/CT - Operational Amplifier with Digital Adjustement of Structural Features The Microelectronics Group of Federal University of Santa Maria (Gmicro) presents the Operational Amplifier with Digital Adjustment of Structural Features. This mixed-signal project brings a novel technique for correction of randomic mismatching caused by manufacturing errors in symmetry-dependent circuits. It is achieved by implementing multiple equal sized analog transistors in an array, then individually selecting them by digital configuration.   UFSM/GMICRO - Full Duplex Internet Protocol Version 4 Implementation The core that is been implemented is a full duplex partial implementation of Internet Protocol version four. It includes most of the requirements needed to work as gateway between two networks, performing tasks of addressing, routing, fragmentation and reassembly. In addition, our IPv4 IP-core partially implements the ICMP (Internet Control Messages Protocol) and the ARP (Address Resolution Protocol).   UNESP - Filters For Digital Image Processing We design a system that aims at producing an image analysis environment in which a set of hardware optimized filters are to be implemented on an integrated circuit. The interconnection of such filters is to be programmed so that the user can choose which filters to use in his or her application as well as the sequence in which they are to be applied during the analysis.   UNICAMP - xxx   UNIFEI - Flash Memory Reading Controller This project will allow the data retrieval from flash memories into a circuit or bus, to be used by an external circuit or device. The controller is comprised mainly of registers, address decoders, and clock and control signals to assure proper synchronization. The project goal is have a fast memory data retriever circuit to be integrated into a larger system.   UNIPAMPA - Floating Point Unit 32 Bits Single Precision IEEE 754 Standard   UNIVALI - LIN Slave Interface The LIN-Bus Core Project aims at developing a synthesizable LIN (Local Interconnect Network) bus slave interface for use in automotive networks, receiving and transmitting messages in a LIN network. It is intended to be used for applications including low cost automotive networks, interfaces for sensors and actuators, and other applications. This project is inserted at the Brazil IP Program and it is sponsored by CNPq, a Brazilian Federal Research Agency.